During integrated circuit manufacture, semiconductor wafers used in semiconductor fabrication typically undergo numerous processing steps, including deposition, patterning, and etching steps. Details of these manufacturing steps for semiconductor wafers are reported by Tonshoff, et al., “Abrasive Machining of Silicon”, published in the Annals of the International Institution for Production Engineering Research, (Vol. 39/2/1990), pp. 621-635. In each manufacturing step, it is often necessary or desirable to modify or refine an exposed surface of the wafer in order to prepare the wafer for subsequent fabrication or manufacturing steps.
For example, after a deposition step, the deposited material or layer on a wafer surface generally needs further processing before additional deposition or subsequent processing occurs. In another example, after an etching step, there is often a need to deposit either, or both, conducting or insulating materials in layers on the etched surface areas of a wafer. A specific example of this process is used in metal Damascene processes.
In the Damascene process, a pattern is etched into an oxide dielectric layer. After etching, optional adhesion/barrier layers are deposited over the entire surface and then a metal is deposited over or on top of the adhesion/barrier layers. The deposited metal layer is then modified, refined or finished by removing the deposited metal and regions of the adhesion/barrier layer on the surface. Typically, enough surface metal is removed so that the outer exposed surface of the wafer comprises both metal and an oxide dielectric material. A top view of the exposed wafer surface should reveal a planar surface with metal corresponding to the etched pattern and dielectric material adjacent to the metal. The metal(s) and oxide dielectric material(s) located on the modified surface of the wafer inherently have different physical characteristics, such as different hardness values. An abrasive article used to modify a wafer produced by the Damascene process must be carefully designed so as to simultaneously modify the materials without scratching the surface of either material. Further, the abrasive article must be able to create a planar outer exposed surface on a wafer having an exposed area of a metal and an exposed area of a dielectric material.
Such a process of modifying the deposited metal layer until the oxide dielectric material is exposed on the wafer outer surface leaves little margin for error because of the submicron dimensions of the metal features located on the wafer surface. It is clear that the removal rate of the deposited metal must be fast to minimize manufacturing costs. Further, metal removal from areas which were not etched must be complete. Still further, metal remaining in etched areas must be limited to discrete areas or zones, and the remaining metal must be continuous within an area or zone to ensure proper conductivity. In short, the metal modification process must be uniform, controlled, and reproducible on a submicron scale.
One conventional method of modifying or refining exposed surfaces of wafers employs methods that treat a wafer surface with a slurry containing a plurality of loose abrasive particles dispersed in a liquid. Typically this slurry is applied to a polishing pad and the wafer surface is then ground or moved against the pad in order to remove or take off material on the wafer surface. Generally, the slurry also contains agents which chemically react with the wafer surface. This type of process is commonly referred to as a chemical-mechanical planarization or polishing (CMP) process.
One problem with CMP slurries, however, is that the process must be carefully monitored in order to achieve a desired wafer surface topography. Another problem is the mess associated with loose abrasive slurries. Another problem is that the slurries generate a large number of particles that must be removed from the surface of the wafer and disposed of following wafer treatment. Handling and disposal of these slurries involves additional processing costs for the semiconductor wafer fabricator.